(1) Field of the Invention
The present invention relates to an address input circuit which divides the storage area of a semiconductor memory device into smaller capacity areas than the original without changing its circuit configuration and allows each divided area to be selected without changing any circuit configuration. The present invention also relates to a semiconductor memory using this address input circuit.
(2) Description of the Prior Art
As a conventional technology of semiconductor memories, Japanese Patent Application Laid-Open Sho 59 No.40392 discloses a semiconductor memory which, if it has any defective cell, can be used as a memory having a smaller storage capacity by discarding the defective portion. This device will be described hereinbelow with reference to the drawings.
FIG. 1 shows an address input portion on the upstream side of a semiconductor memory. Reference numerals 11-1 to 11-n designate address input terminals (to be referred to hereinbelow as pins) to which address data A0-An are supplied. Provided for each pin 11-0 through 11-n is an address buffer 12-0 through 12n which outputs a pair of address data values A0/A0, A1,/A1, . . . An,/An, having a complementary relationship therebetween based on address data values A0-An.
Inserted between each pin 11-0 through 11n and a corresponding address buffer 12-0 through 12-n is an enhancement-mode MOSFET 13-0 through 13-n. Further, an enhancement-mode MOSFET 14-0 through 14-(n-1) is inserted between each pin 11-0 through 11-(n-1) and the input terminal to each address buffer 12-1 through 12-n, which is more significant by one bit.
All the control gates of MOSFETs 13-0 to 13-n are connected to a common line 15 while all the control gates of MOSFETs 14-0 to 14-(n-1) are connected to a common line 16.
One of these lines, i.e., line 15 is connected at its upper end in the drawing, to a depletion-mode MOSFET 17, which in turn is connected to a Vcc supply which supplies a positive power source voltage Vcc. The gate of this MOSFET 17 is connected to the Vcc supply. The bottom end in the drawing of the line 15 is connected to a depletion-mode MOSFET 18, which in turn is connected to a Vdd supply which supplies a standard power source voltage Vdd. The gate of this MOSFET 18 is connected to the Vdd supply.
The dimensions of the two MOSFETs 17 and 18 are set appropriately so that line 15 residing between the two can be kept at the logical `1` level.
The other line, line 16 is connected at its upper end in the drawing, to a depletion-mode MOSFET 19, which in turn is connected to the above Vcc supply. The gate of this MOSFET 19 is also connected to the Vcc supply. The bottom end in the drawing of the line 16 is connected to a depletion-mode MOSFET 20, which in turn is connected to the above Vdd supply. The gate of this MOSFET 20 is also connected to the Vdd supply. The dimensions of the two MOSFETs 19 and 20 are set appropriately so that line 16 residing between the two can be kept at the logical `0` level.
FIG. 2 shows an address data fixing circuit which is provided for each address data output terminal of address buffer 12-0 through 12-n. This address data fixing circuit is composed of two enhancement-mode MOSFETs 31 and 32 so that the output data values Ai,/Ai can be fixed at in accordance with the control signals F11 and F12 regardless of the address data being given to the output terminal.
In the above configuration, in a normal state, all the MOSFETs 13-0 to 13-n are being turned on while all the MOSFETs 14-0 to 14-(n-1) are being turned off, so that the address data A0 through An being supplied at pins 11-0 through 11-n are transmitted by way of respective MOSFETs 13-0 through 13-n, which are all in the on-state, to the corresponding input terminals of address buffers 12-0 through 12-n.
In this case, based on address data A0 through An, any of the memory cells (not shown) can be selected. That is, this case is free from any defective memory cell.
FIG. 3 is a diagram showing a memory cell array. It is assumed that the left half of the cell array is selected by An=0 and the right half is selected by An=1. If the X-area in this figure, i.e., the area designated by An=0 has a defective memory cell, control signal F12 supplied to the address fixing circuit shown in FIG. 2 in address buffer circuit 12-n is set at `1`. This causes An to be `0` and/An to be `1` regardless of the address data being supplied to pin 11-n, so that the memory area designated by An=1 will not be selected. Therefore, in this case, this memory cell array can be used as a device having half the storage capacity of the original memory cell array.
As stated with reference to FIG. 1, the level of line 15 is kept at the logic `1` by MOSFETs 17 and 18 while the level of line 16 is kept at the logic `0` by MOSFETs 19 and 20. In this case, when there exists no defective bit in the memory area or in other words, when the entire original storage capacity is utilized, currents will flow through lines 15 and 16. Therefore, use of this conventional circuit configuration gives rise to a problem of extra current consumption.
Further, when the memory is used in a mode that allows partial or smaller capacity than the original capacity to be used, or when a certain address value is fixed, it is necessary to generate control signals F11 and F12 to be supplied to the address data fixing circuit which is provided for each address data output terminal of address buffer 12-0 through 12-n. In this case, the circuit for generating control signals F11 and F12 should be built in on the chip or the signals have to be input externally.
If the circuit for generating signals F11 and F12 is provided within the chip, an extra area is needed for that, resulting in increase in chip area and manufacturing cost. Alternatively, even when control signals F11 and F12 are input from an external logic, there occurs a similar problem as well as other extra problems such as the memory cannot be used individually, and the like.